preliminary ? 2001 fairchild semiconductor corporation ds500654 www.fairchildsemi.com september 2001 revised december 2001 fin1101 lvds single port high speed repeater (preliminary) fin1101 lvds single port high speed repeater (preliminary) general description this single port repeater is designed for high speed inter- connects utilizing low voltage differential signaling (lvds) technology. it accepts and outputs lvds levels with a typical differential output swing of 350 mv which pro- vides low emi at ultra low power dissipation even at high frequencies. it can directly accept lvpecl, hstl, and sstl-2 for translating directly to lvds. features greater than 800 mbps full differential path 3.5 ps max random jitter and 135 ps max deterministic jitter 3.3v power supply operation wide rail-to-rail common mode range ultra low power consumption lvds receiver inputs accept lvpecl, hstl, and sstl-2 directly power off protection 6 kv hbm esd protection meets or exceed the ta/eia-644-a lvds standard packaged in 8-pin soic and us8 (preliminary) open circuit, shorted, and terminated fail safe protection ordering code: devices also available in tape and reel. specify by appending suffix letter ?x? to the ordering code. connection diagram functional diagram pin descriptions function table h = high logic level l = low logic level x = don't care z = high impedance order number package number package description fin1101m m08a 8-lead small outline integrated circuit (soic), jedec ms-012, 0.150" narrow FIN1101K8 mab08a 8-lead us8, 0.7mm x 3.1mm x 2.0mm pin name description r in + non-inverting lvds inputs r in ? inverting lvds inputs d out + non-inverting driver outputs d out ? inverting driver outputs en driver enable pin v cc power supply gnd ground inputs outputs en r in + r in ? d out + d out ? hhlhl hlhlh h fail safe case h l l or open x x z z
preliminary www.fairchildsemi.com 2 fin1101 absolute maximum ratings (note 1) recommended operating conditions note 1: the ? absolute maximum ratings ? : are those values beyond which damage to the device may occur. the databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature and output/input loading variables. fairchild does not recommend operation of circuits outside databook specification. dc electrical characteristics over supply voltage and operating temperature ranges, unless otherwise specified note 2: all typical values are at t a = 25 c and with v cc = 3.3v. supply voltage (v cc ) ? 0.5v to + 4.6v lvds dc input voltage (v in ) ? 0.5v to + 4.6v lvds dc output voltage (v out ) ? 0.5v to + 4.6v driver short circuit current (i osd ) continuous 10 ma storage temperature range (t stg ) ? 65 c to + 150 c max junction temperature (t j )150 c lead temperature (t l ) (soldering, 10 seconds) 260 c esd (human body model) 6000v esd (machine model) 600v supply voltage (v cc ) 3.0v to 3.6v magnitude of differential voltage (|v id |) 100 mv to v cc operating temperature (t a ) ? 40 c to + 85 c symbol parameter test conditions min typ max units (note 2) v th differential input threshold high see figure 1 100 mv v tl differential input threshold low see figure 1 ? 100 mv v ih input high voltage (en) 2.0 v cc v v il input low voltage (en) gnd 0.8 v v od output differential voltage 250 350 450 mv ? v od v od magnitude change from r l = 100 ? , driver enabled, 25 mv differential low-to-high see figure 2 v os offset voltage 1.125 1.25 1.375 v ? v os offset magnitude change from 25 mv differential low-to-high i os short circuit output current d out + = 0v & d out ? = 0v, driver enabled ? 8ma v od = 0v, driver enabled 6ma i in input current (en, d inx + , d inx ? )v in = 0v to v cc , 20 a other input = v cc or 0v (for differential inputs) i off power-off input or output current v cc = 0v, v in or v out = 0v to 4.6v 20 a i ccz disabled power supply current drivers disabled 5 ma i cc power supply current drivers enabled, any valid input condition 15 ma i pu/pd output power-up/ v cc = 0v to 1.5v 20 a power leakage current i oz disabled output leakage current driver disabled, d out + = 0v to 4.6v or 20 a d out ? = 0v to 4.6v v ic common mode voltage range v id /2 v cc ? (v id/ 2) v c in input capacitance 3pf c out output capacitance 4pf
preliminary 3 www.fairchildsemi.com fin1101 ac electrical characteristics over supply voltage and operating temperature ranges, unless otherwise specified note 3: all typical values are at t a = 25 c and with v cc = 3.3v. note 4: t sk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction (either low-to-high or high-to-low) when both devices operate with the same supply voltage, same temperature, and have identica l test circuits. note 5: passing criteria for maximum frequency is the output v od > 250 mv and the duty cycle is better than 45% / 55% with all channels switching. symbol parameter test conditions min typ max units (note 3) t plhd differential propagation delay 0.8 1.8 ns low-to-high t phld differential propagation delay r l = 100 ? , c l = 5 pf, 0.8 1.8 ns high-to-low v id = 100 mv to 1100 mv, t tlhd differential output rise time (20% to 80%) v ic = v id /2 to v cc ? (v id /2), 0.29 0.58 ps t thld differential output fall time (80% to 20%) duty cycle = 50%, 0.29 0.58 ps t sk(p) pulse skew |t plh - t phl | see figure 3 and figure 4 0.2 ns t sk(pp) part-to-part skew (note 4) 0.5 ns f max maximum frequency (note 5) 800 mbps t pzhd differential output enable time from z to high 10 ns t pzld differential output enable time from z to low r l = 100 ? , c l = 5 pf, 10 ns t phzd differential output disable time from high to z see figure 5 and figure 6 10 ns t plzd differential output disable time from low to z 10 ns t dj lvds data jitter, v id = 300 mv, prbs = 2 23 ? 1, 100 135 ps deterministic v ic = 1.2v at 800 mbps t rj lvds clock jitter, random v id = 300 mv 2.2 3.5 ps (rms) v ic = 1.2 v at 400 mhz
preliminary www.fairchildsemi.com 4 fin1101 required specifications: 1. when the true and complement lvds outputs (having a 100 ? connected between outputs) are connected to 3.75k ? resistors and the common point of those 3.75k ? resistors are connected to a voltage source that sweeps from 0v to 2.4v, the dc v od and ? v od are still maintained (see figure 1). 2. when the true and complement lvds inputs are con- nected together to a voltage source that sweeps from 0v to 2.4v with respect to the common ground, then the absolute value of the difference in input leakage current is less than 6 a (see figure 2) 3. pull-down resistor is required on the enable (en) input. 4. human body model esd and machine model esd should be measured using mil-std-883c method 3015.7 standard. 5. latch-up immunity should be tested to the eia/jedec standard number 78 (eia/jesd78). 6. when the true and complement lvds outputs are con- nected with 49.9 ? resistors each to common point, then the common point does not vary by more than 150mv under all process, temperature, and voltage conditions when the outputs switch either from low-to-high or from high-to-low (see figure 3, c l = board + pin stray capacitance) 7. when the lvds inputs are not driven either in high impedance, shorted together, or terminated with a resistor, the outputs go the high state (d out + = h, d out ? = l) and the lvds inputs do not sink or source more than 20 a. figure 1. common mode supply test circuit figure 2. receiver input balance measurements figure 3. dynamic v os test circuit and waveforms figure 4. differential receiver voltage definitions and propagation i and transition time test circuit
preliminary 5 www.fairchildsemi.com fin1101 required specifications: (continued) figure 5. differential driver dc test circuit note a: all input pulses have frequency = 10mhz, t r or t f < = 1ns note b: c l includes all probe and jig capacitances figure 6. differential driver propagation delay and transition time test circuit figure 7. ac waveforms note a: all input pulses have frequency = mhz, t r or t f < = 2 ns note b: c l includes all probe and jig capacitances figure 8. differential driver enable and disable test circuit figure 9. enable and disable ac waveforms
preliminary www.fairchildsemi.com 6 fin1101 physical dimensions inches (millimeters) unless otherwise noted 8-lead small outline integrated circuit (soic), jedec ms-012, 0.150" narrow package number m08a
physical dimensions inches (millimeters) unless otherwise noted (continued) preliminary 7 www.fairchildsemi.com fin1101 lvds single port high speed repeater (preliminary) physical dimensions inches (millimeters) unless otherwise noted (continued) 8-lead us8, 0.7mm x 3.1mm x 2.0mm package number mab08a (preliminary) fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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